module seg_num(      //数码管显示模块：选择数码管0-4共5个数码管显示{A1，A0，RNG，DATA}
//端口信号：模块的输入输出接口
	input         clk,   //系统时钟50MHz 
	input         rst_n, //低电平复位
	input  [19:0]  data_in, //20位输入数据
	
	output reg [7:0] seg,   //数码管段选
	output reg [2:0] sel    //数码管位选
	);

	//通过查找表的方式，将相应位的数码管与数据的相应位一一对应
	reg [3:0]  num;   
	always@(*)
		case(sel)     
			4: num = data_in[3:0];    //第五个数码管显示数据的低四位[3：0]
			3: num = data_in[7:4];    //第四个数码管显示数据的低四位[7：4]
			2: num = data_in[11:8];   //第三个数码管显示数据的低四位[11:8]
			1: num = data_in[15:12];  //第二个数码管显示数据的低四位[15:12]
			0: num = data_in[19:16];  //第一个数码管显示数据的低四位[19:16]
			default:;
		endcase

	//通过查找表的方式，将数据与数码管的显示方式一一对应	
	always@(*)	
		case(num)
			0:  seg <= 8'hC0;  	//8'b1100_0000
			1:  seg <= 8'hF9;	//8'b1111_1001
			2:	 seg <= 8'hA4;	//8'b1010_0100	
			3:  seg <= 8'hB0;	//8'b1011_0000
			4:  seg <= 8'h99;	//8'b1001_1001
			5:  seg <= 8'h92;	//8'b1001_0010
			6:  seg <= 8'h82;	//8'b1000_0010
			7:  seg <= 8'hF8;	//8'b1111_1000
			8:  seg <= 8'h80;	//8'b1000_0000
			9:  seg <= 8'h90;	//8'b1001_0000
			default:seg <= 8'hFF; //8'b1111_1111
		endcase
		
	//计数器时钟分频：用cnt第10位的变化作为分频时钟	
	reg [23:0]  cnt;			
	always@(posedge clk or negedge rst_n) 
		if(!rst_n)
			cnt <= 4'd0;
		else
			cnt <= cnt + 1'b1;
	//在分频时钟下，数码管的0-5位依次循环
	always@(posedge cnt[10] or negedge rst_n)   //分频时钟为2^10/50M
		if(!rst_n)
			sel <= 0;
		else if(sel < 4)
			sel <= sel + 1'b1;
		else
			sel <= 0;	
		
endmodule 